Central data processor for computer system having a divided memory



Feb. 4. 1969 H. B. MARX ETAL CENTRAL DATA PROCESSOR FGR COMPUTER SYSTEMHAVING A DIVIDED MEMORY Sheet of Filed Feb. 14. 1966 Feb. 4. 1969 H. a.MARX ETAL 3 CENTRAL DATA PHQCESSQR FR COMPUTER SYSTEM HAVING A D IVIDEDMEMDRY ?iled Feb. 14, 1966 Sheet of a INSTRUCTION WORD CM PX I R V M L PFlg.2

DATA WORD 5 MAGNITUDE P INDEX REGISTER SX 0R M5 MV XV P TX INDIRECTADDRESS PX I L P F/ 20 mvsmons.

HANSRMARX EDWARD w- MOLL BY BRUCE w. mmmc MEYER SCHILDER PJIJZIJ ATT NEYFeb. 4. 1969 H. a. MARX ETAL CENTRAL DATA PROCESSOR FOR COMPUTER SYS'IEMHAVING A DIVIDED MEMORY Sheet Filed Feb. 14 1966 Feb. 4. 1969 H. a. MARXTAL 3426329 CENTRL DATA PFOUESSR F COMPUTER SYSTEM HAVING DIVIDED MEMORYFiled Feb. 14, 1966 Sheet 4 of 6 mama PER\OD 4A l|22355T45566778D88899 il22555T4556678D88 899 United States Patent O Claims ABS'I'RACT OF THEDISCLOSURE A data processor for use in a computer system including aplurality of memory units and incorporating arithmetic and programexecution elements and a plurality of memory selection registersresponsive to command bits fewer in number than that required to countthe memory units, to enable access to a selected one of them.

The present invention relates to a computer which may be the centraldata processor ncorporated in a computer system which may be modular andmay be employed with a memory dividecl into modules or units, or othermemory divisions. More particularly, the present invention relates to asynchronous computer comprising the arthmetic and program execution unitof an expansible modular computer system in which parallel arithmeticoperations and parallel transfers are effected and wherein primary andsecondary register means are incorporated to provide capability ofaddressing a plurality of memory units with command words in which arelatively few bits can select one memory unit of a larger number ofmemory units than is possible from the count atforded by the fewernumber of bits. For example, using a single bit of a command word theinventive data processor may address up to eight memory units. Thepresent invention further provides timc-saving circuitry enablingby-pass of paths through certain registers thus providing time-savingand eliminating time delay which would otherwise occur due toutilization of the register logic in operations Where such registers arenot employed. The computer of tliis invention is relatively light,rugged and otherwise suitable for incorporation into a system intendedto be transportable over various types of terrain, in or on water, inthe atmosphere, or in outer space. The central data processor of theinvention described herein incorporates improvements in many of thefeatures and circuits described in copending application Ser. No.527,374, for Central Data Processor," filed simultaneously by the sameinventors and assigned to the assignee of the present invention.However, the computers of ths invention and of the simultaneously filedapplication are separately developed computers and perform functionsseveral of which are similar and possess some circuits and featureswhich are similar but the implementing circuits and structure also dfierconsderably in many aspects and the present invention provides severalnew and several improved features additional to those provided by theinvention of the copending patent application.

Data processors wherein computing functions are separately performed areincorporated as portions of large scale computer systems. Examples ofsuch large scale com puters are the modular computers of the systems ofBurroughs Corporation, known popularly as the D825 and 138500 Burroughscomputer systems, the computer portion of a system known as the S2000Transac Computer and the so-callecl Master and Slave computer of asystem known as the RW400, polymorphic computer. However,

3,426329 Patanted Fel). 4, 1969 these systems are essentially largerscale and more permanently located systems and are not directedessentially to uses which require features of the present inventionwhich, for example, make it adaptable tor portable use on land includingrugged terrain, in the air, on and under water, and in space While thesecomputers present refiuements which are very desirable for manyapplications, they do not provide some features of the present inventionwhich make it adaptable to communication selectability within andwithout the central data processor modules. They do not have certainfeatures of the present invention which because of some of its intendeduses require high concentration of circuitry and avoidance of redundantcircuits and circuits essential to the purposes of this invention, andwhich avoid time delay in the performance of certain commancls and theexecution of certain phases and processes.

The data processor of the present invention overcomes the disadvantagesof other computers and is adaptable to be made rugged and portable, itemploys reduced circuitry for the functions accomplished, it providesfor lesser numbers of bits required in the instruction words to performthe same functions and it avoids time delay or specific commandexecution.

The central data processor of the invention presents advantages in itsincorporation of improvements in interconnection and in circuitry suchthat a substantial saving in intermodular wiring and communicationcircuits is ef fectecl. The invention advantageously employs selectionregisters to provide selection of one of a plurality of memory moduleswherein only one bit of the instruction word is required by theprogrammer for that purpose. The pres ent invention further providesspecial logic and time saving circuitry wherein inputs of certainregisters are carried along further provided paths rather than from theoutput and through their internal logic where time delay would otherwisebe deleterious, thereby gaining time advantage when necessary withoutsacrifice of the advantages of the operation faclities of theseregisters when they are required to be in the path of execution.

Accordingly, an object of the present invention is to provide a centra]data processor for a modular computer system which is reliablyemployable in space, on and under water, in the air and on the ground,in a movable vehicle despite variations of ambient conditions, which issuitable both for commercial and military use, which is light, portableand provides economy in circuits and in the avoidance of many of thecircuits utilized, and which avoids time delay.

Another object of the present invention is to provide a data processorunit incorporating circuitry providing flexible indexing whereinindexing may be automatically accomplished without additional programsteps except specifying indexing and incorporating improved features ofrelocating index registers in memory under program control.

Another object of the data processor or computer module of the presentinvention is to provide simplified and improved circuitry which enablesexecution of instructions wherein only a single bit of the instruction,rather than a plurality of at least three bits, can specify a particularone of a plurality, for example, up to eight memory modules, andsimlarly, a lesser number of bits than would normally be required byabilty to count from the number of bits can specify one or a groupWithin a greater plurality of memory units.

Another object of the invention is to provide circuitry wherein aplurality, for example, two registers, a primary and a secondaryselection register, etc. may be set up under program control and may beused to define the two, for example, memory units which may be directlyaccessed by the command word and to enable specifying without increasingthe amount of bits required in the command the one or ones of all thememory units which are selected for access.

Still another object of the present invention is to provide a flexiblemeans of automatically addressing any one of a plurality, for example,up to eight memory units, wherein one of two memory units ma\ heselected by a sing e bit of a word, and wherein structure is providedsuch that if one of the six additiottal memory modules is desired to beselected, this may be accomplished by indexing or indirect addressing,and which flexible means may be means utilizing a comparatively lessernumber of bits in a word than would define the total number of memoryunits available to be accessed to identify which one or ones of all thememory units is selected for access.

Another object of the present invention is to provide a central dataprocessor in which is incorporated a spe cial logic unit, for example, aprogram counter and/or address field register logic and attendantmechanisms whereby the time normally consumed and/or the extra logiccircuits normally provided for the contents of these logic units, issaved by providing means connectiug the logic unit inputs, of theprogram counter and the address field register, for example, directlyinto a memory address multiplex unit, rather than causing delay byprocessing the outputs of these logic units with consequent loss of timeand/or additional apparatus required.

Another object of the invention is to provide a central data processorwhich incorporates logic and circuits such that a programmer can providea large number and variation of commands with a relatively small amountof circuitry.

Wl1ile the novel and distinctive features of the invention areparticularly pointed out in the appended claims, a more expositorytreatment of the invention, in princi ple and in detail, together withadditional objects and advantages thereof, is afiorded by the followingdescription and accompanying drawings in which:

FIGURE 1 is a block diagram of a first preferred i1- lustrativeembodiment of the central data processor of the present invention;

FIGURE 2A is a diagrammatic representation of the format for theillustrative embodiment of FIGURE 1;

FIGURE 28 is a diagrarnrnatic representation of the format for the wordorganization of a data word employable with the illustrative embodimentof FIGURE 1;

FIG. 2C is a diagramrnatic representation of the format for the wordorganization of an index register word employable with the illustrativeembodiment of FIG. 1;

FIG. 2D is a diagrammatic representation of a format for the wordorganization of an indirect address word employable with the illustratveembodiment of FIG. 1;

FIG. 3 is a block schematic diagram of the timing counter of theillustrative embodiment of FIG. 1 illustrating also timing flow in flowchart representation;

FIG. 4A is a master chart comprising a grid with subdivisioncorresponding to the timing intervals employed in instruction executionand plotting the timing intervals employed for execution versusparticular commands in the illustrative embodiment of FIG. 1 and showingadaptation to a memory having a four-microsecond cycle time by way of.example of employment of one possible type of memory with theillustrative embodiment of FIG. 1;

FIG. 4B is a diagrammatic representation illustrating an indexingmodification cycle for the system of FIG. 1 and in accordance with FIG.4A;

FIG, 4C is a diagrammatic representation iilustrating an indirectaddressing cycle for the system of FIG. 1 and in accordance with FIG.4A;

FIG. 4D is a representation of the key describing the command-timinginterval subdivision component boxes of the chart of FIG. 4A;

FIG. 5 is a logic diagram of the circuits of bits 7 through 12, forexample, of the adder of the illustrative embodiment of FIG. 1;

FIG. 6 is a logic diagram of the bit 3 circuit, for example, of the Aregister of the illustrative ernbodiment of FIG. 1;

FIG. 7 is a logic diagram of the bit 5 circuit, for example, of thecircuits of the data output multiplex unit of the illustrativeembodiment of FIG. 1;

FIG. 8 is a logic diagram of the bit 19 circuit, for example, of theaddress field register of the illustrative embodiment of FIG. 1; and

F1G. 9 is a logic diagram illustrating a portion of the circuit forlook-ahead subcommand generation of the il lustrative embodiment of FIG.1.

The term I/O is used throughout the specification and drawings as anabbreviation of input and output. Now refer to the drawings and inparticular to FIG. l.

As shown in FIG. 1, the block diagram of the illustrative embodiment ofthe centra] processor of the invention, there are providcd a data inputregister (DIR) a parity check device 101, an adder logic circuit 103, adata output multiplex (DOM) unit 104, a register check circuit 105, atiming and control unit 106, an A register 107, a C register 108, anoperation register 109, a parity generator 110, a memory addressmultiplex unit 115, an address field register 116, a program counter117, 2111 index location register 118, primary and sccondary selectionregisters 119, a subcommand matrix 120, and a com mand decoder 121.

The data input register (DIR) 100 may comprise 25 flip-flops andassociated drivers. The data input register 100 holds (as 25-bit words)all data coming to the centrul data processor from all external sourcesincluding memory and I/O s0urces. The 25-bit words include 24 bits,which is the basic word length of the words in the machine plus 21parity check hit. The parity check device 101 is responsive to theparity check hit in the data input register 100. The parity check device101. checks the register 100 for odd parity and if parity does not checkit provides an error signal to the timing and control logic 106 whichwill be described hereinafter. The adder logic circuit 103 is a 23-bitadder which is connected to and responsive to the 23-bit output from thedata input regis ter 100. Adder logic circuit 103 is also connected toand responsive to the output of data output multiplex unit 104. The 23bits the adder logic circuit device 103 looks at are the leastsignificant 23 bits from the data input regis ter 100 and from the dataoutput multiplex unit 104. By the 23 least significant bits is meant the23 least significant hits of the actual 24bit word (less parity); the25- bit word includes the parity bit which really is in the leastsignificant bit position. The most significant bit of a computer word inthe illustrative emhodiment machine is usually the sign bit. The adder103 is a parallel adder incorporating both ripple carry (ripple downcurry) and group carry in groups of 8, 7 and 8 (a total of 23). Withinthese 8-, 7* and 8-group carries, a subgroup carry of 4 bits isprovided, as will be described hereinafter. The adder logic 103comprises exclusive OR circuitry, The register check circuit 105 isconnected to be responsive to the exclusive OR outputs of adder logic103. The register check circuit 105 detects a condition wherc all 23bits of the exclusive OR output of adder logic 103 are ones (1) andsends a sigma] in that event to the timing and control unit 106. Theregister check circuit 105 checks the equality of any input to the datainput register 100 with the contents of a register selected by the dataoutput multiplex unit 104 for comparison. 'l'his check is used in manyinstructions, for cxample, wherein a condition is imposed, if equal.

The arithmetic unit of the centra] data processor comprises tworegisters: the A register 107 and the C register 108, The circuit ofeach of the A register 107 and C register 108 compriscs 24 flip-flopsand the associated gate circuitry. The input gates to each of the Aregister 107 and the C register 108 permit data input, shift right,shift left and an ANDing of the contents of the A or C register 107 or108 and the data input. Although the A register 107 and the C registor108 are utilized as two separate accumulators for the adder logic 103,they can be combined for double precision operation. Not only themultiply and divide operations which conventionally are executed usingdouble precision may be so employed, but in addition, double preeisionadd and subtract may be effected utilizing the A register 107 and the Cregister 108.

The data output multiplex unit (DOM) 104 comprises two sections: Onesection is a multiplex section which is capable of enabling one or moreof the registers of the machine to provide outputs to it; that is. theDOM 104 enables the gates to receive the contents of any of theregisters of the machine into it except an operation register (OP) 109which will be described. The other section of the data output multiplexunit 104 selects either the true state or the complement state of thedata provided by the first described multiplex section. When it isdecided to accept inputs from one of the other registers in the centralprocessor, the second seetion of the data output multiplex unit 104either communicates the true contents of the register straight throughthe data output multiplex unit 104 or communicates the inverse of thecontents of the register which is fed into a succeeding unit. Theseconcl section of the data output muitiplex unit 104 can also be usedto inhibit all inputs even tbough the first seetion of the data outputmultiplex unit 104 has enabled a register to provide inputs to the dataoutput multiplex unit 104. This provides a dual control feature, Thedata output multiplex unit 104 also eomprises drivers which providepower to send the data to the ex ternal units from the central dataprocessor such as to the memory and I/O control units of the system. Asmentioned hereinabove, the data output multiplex unit 104 also suppliesone of the inputs to the adder logic unit 103. The parity generatorcircuit 110 generates odd parity on all words eoming from the dataoutput multiplex unit 104 and provides the 25th or parity bit requiredfor transfers into memory and into the UO control modules. Thus, anytime data is sent from the eentral data proc essor, the word has parity.

The address and control section is shown generally in the right-handportion of FIG. 1. The memory address multiplex unit 115 comprises al-bit multiplex unit with associated driver circuits. It is used forsending all 21ddresses from the central data processor through aregistcr in the I/O eontrol unit from whence they are sent to the memorymodules. This transfer is further described in the co-pending applcationScr. No. 527,350 filed Feb. 16, 1966, for Modular Computer System," ofHans Marx, and assigned to the assignee of the present invention. Thiseo-pending application is incorporated by refcrence in the presentapplication and supplements the disclosure herein.

Each bit of the bits inserted in the memory address multiplex unit 115can come from any one of four registers within the computer. Theseregisters are the data input register 100, the adtlress field register116 to be described, the program counter 117 to be described, or theindex location register 118 to be deseribed. Provision is made withinthe memory address multiplex unit 115 to inhibit any output from thisunit. This line is generally not used in the eentral data processorexcept when the central data processor is one of several processorswhich will be utilized in the system. al] of which have access to thememory sueh that the memory is shared. This line of the memory addressmultiplex unit 115 is also used if a bufered 1/O channel is sharingaccess to memory with the eentral data processor. This occurs in some ofthe systems which employ the computer of this invention and which aredescribed in the above-mentioned copending application of Hans Marx forModular Computer Systern.

The address field register 116 is a 15-bit flipflop register whichineorporates eircuitry to give it a capability of being used as acounter. The address field register 116 eontains either the address of adata word to be operated upon, or where there is no data word requiredit contains variation bits which modify a command word sueh thatdifferent options of the commancl may be executed. When employed as acounter the address field register 116 is used to count sequentialaddresses for bleek testing or it counts iterative steps for logicoperations (in the divide operation or multiply operation, for examplc)and in both cases the address field register 116 counts up from zerountil a preseleeted number is detected. Thus, in a divide operation itis known in 116 counts up from zero until a prescleeted number isdetected. Thus, in a divide operation it is known in advance by thedivisor how many steps there are, e.g. 23 steps. The address fieldregister 116 is used in this application as an adjunct to the timingcounter which is a portion of timing and control unit 106. The addressfield register 116 is fed from (1) the primary anti secondary selectionregisters unit 119, (2) the output of the adder logic 103, and (3) theoutput of the data input register 100. Primary and secondary selectionregisters 119 comprise two 3-bit flip-flop registers. These registersare used to define the two active memory modules which may be selecteddirectly by one bit of a command. Either or both registers of theprimary and secondary selection registers 119 can be loaded or changedunder program control from the information which is fed in from the datainput register 100.

The program counter 117 contains 15 flipflops and associated counterlogic. The program counter 117 sequentially counts up the addressescontained in each of the sequential instruction words. Program counter117 can be loaded either from the data input register or from the adderlogic 103. Eithcr the input from the data input register 100 or theinput from the adder logic 103 can be utilized for branching operations.

Circuit means to be described are provided in the com pater of theinvention whereby the input to the program counter (P) 117 optionally isfed directly into the memory address multiplex unit to eliminate timeloss when efleetng brunch operations.

The index location register (XL) 118, a l3bit flipilop register, isprovided for indexing. The 13 bits of the index location register 118provide the most significant 13 bits of a 15-bit address. The leastsignificant two bits of the address which are added to make the 15-bittotal address are seleeted from two bits taken from the data inputregister 100. when the data input register 100 contains an instruclionword, an index word, or an indirect address word. Any one of these l5hitwords in the DIR 100 contains two bits which specify that indexing willbe effected if either bit is a l. Further, if either of these two bitsis a l, which specifies that indexing is to occur, they form the leastsignificant two bits of the address word which two bits when added tothe 13 bits of the index location register 118 form the address word.Thus, a 15bit word is formed from the two bits specifying that indexingshould be done, that is, one of the two bits being a l, plus the moresignificant 13 bits provided by the contents of the index loeationregister. This 15-bit word specifies the iocation in main memory wherethe index word is stored. Since one of the two (least significant) bitsmust be a 1 there are only three index registers aetive at one time.That is, there are only three possible index registers which ean beselected from the 13-bit contents of the index location register 118plus the two losser significant bits taken from the word stored in thedata input register 100.

When these two bits taken from the data input register 100 are bothzeros, they can be used for special applicatiens. For example, they maybe used in combination with the 13 most significant bits which are thecontents of the index location register 118 in iterative programs wherea portion of the program is to be repeated a number of tmes. In thiscase these two zeroes (referred to hereinafter as the location") plusthe l3-bit word of the index location register 118 defines the locationof the word in memory which counts the number of times of iteration thatthis portion of: the program is repeating. This same location (O0location), that is, the two zeroes (00) which form the least significanttwo bits added on to the contents of the index location register 100,also may be used as an address in main memory in which is stored theaddress which records the results of a successful test of a block ofwords in memory; also, this word gives the number of shifts necessary inperforming a normalizing instruction; this word also forms one of thetwo addresses denot.ing which register is used as one of the tworegisters for temporary storage when it is de sired to shift thelocation of the word in memory from one locution to another location.Additionally, the 00 location, and only this 00 location, specities theaddress in memory which contains an upper or lower boundary limit whichis utilized for testing whether each word of a string of words is withinthe boundary limits which have been predetermined. For example, thecontents of this 00 location may be used for the upper bounds foroperation wherein a word is to be tested against a number of sequentialmemory words to insure that the highest numbered address of the group ofwords to be used has not been passed. (T0 facilitate explanation it isnoted at this point that the illustrative embodiment is a oneaddressmachine.)

The last three aboveenumerated uses (of the index cation register 118contents plus the additional two bits which are taken from the dat-ainput register 100) are so utilized only during the execution of certaininstructions. These certain instructions comprise, for example, the TMX(test or modify index) instruction, the MDT (memory data transfer)instruction, the NMR (normalized register) instruction and the LSP (loadand/or store program counter register) instruction. When one of thesefour instructions occurs the machine looks at the program counter 117 todetermine the address in memory to be fetched. These tour instructions,TMX, MDT, NMR and LSP, cannot be indexed because they will not respondto the presence of a 1 in the least significant two bits of the -bitword made up by the contents (13 hits) of the index location register118 and the data input register 100 two bits, hut rather, instead ofindexing, these four instructions cause this address to be utilized inaccordance with the purposes of the purticular instruction. This featureenables a great amount of versatility to the programmer in utilizationof the word which otherwise wouid be an index word. As statedhereinabove, in block case tests, the 00 indication (bits 6 and 7 arezeros) from the data input register 100 indicates that the XL register118 contents plus these 00 bits point to the address in memory thatcontains the upper bounds. This feature of combining the 13 bits of theindex location register 118 and the two bits in the data input register10!) (bits 6 and 7 of the instruction word) are used not only for thenormal indexing operation, but additionally, in doing a bleek test thisfeature is used to indicate the address in memory in which is stored theaddress of the word which indicates that the block test has beensuccessfully met. Also in the block test this l5-bit composite word (ofthe 13-bit: contents of the index location register 118 With a forced 00ending from the 6th and 7th bits of the instruction word) is used toindicate the upper limit value to signify the location of the end of theblock. Thus, this composite word is used for (1) indexing, (2) to checkfor the limit and (3) to store the address of the word which indicatesthnt the bleek test has been successfully met. These feit tures permitsequential testing of the machine memory,

blocl by block. Also, large groups can be taken, and a number ofsequential blocks can be tested sequentially within this large group forless than, for greater than, or for compare equal to a specified number.This feature enables the one-addresg machine of the illustrativeembodiment when required to exhibit the behavior and to provide theadvantages of a two-address machine.

Refer to FIGS. 2A, 2B, 2C and 2D of the drawings. FlG. 2A is the formatshowing the word organization for the instruction wond. The bits 0-5 arethe command field bits, CM; bits 6 and 7 are the primary index fieldbits, PX; bit 8 is the indirect address selection field bit, I; bit 9 isthe arithmetic register selection field bit, R; bit 10 is the variantfield bit, V; bit 11 is the module selector field bit, M; bits 1223specify the address field, L; and bit 24 is the parity bit, P.

In the data word of FIG. 28 the 0 bit desgnates the sign and bits 123inclusive, represent the magnitude. Bit 24 is the parity bit P. Bit 1 isthe most significant bit of the magnitude.

The index register format is illustrated in FIG. 2C. The index registerformat comprises bits 6 and 7 which are the secondary index field bits,SX (specifies register) or tertiary index bits, TX (specifies register);bit 8, which is the module selector bit MS and which specifies that themodule value designator MV should be substituted for the previous moduleselection; bits 9-11, inclusive, which comprise the module valuedesignator bits MV; bits 12-23, inclusive, which specify the indexvalue, XV; and bit 24, the parity bit P. The SX, TX, MS and MV fieldsare used for control whereas the XV field is the actual index modifier.

FIG. 2D illustrates the format for indirect addressing. Bits 6 and 7 arethe primary index field PX and specify a register. Bit 8 is the indirectaddress bit 1 and specifies the next leve] indirect address. Bits 923specify the address field L.

A description in detail of the individual commands and variations ispresented in the closing section of this application. However, tofacilitate the description herein, a partial list of commands which aprogrammer may em ploy with the computer of the illustrative embodimentand which the bits in the operation register 109 denote is as follows:

Mnemonie Oetnl ende Cornmnnd deseription 30 Add.

10 Adll literal.

Add :nd store.

27 Brunch on contents of memory.

03 Brunch conditionul.

61 Illoelr test for eque.l.

(15 Bleek test for register greater than memory. 64 Bleek test torregister less than memory. 02 Braneh unconditionnl.

06 Control descriptor transfer.

32 Divide.

72 Double precision addition.

73 I)oul le preeisien subtraet.

76 Loe(l U i1d A registers.

36 Land register.

6? Leed end store P register.

37 Land index leention register.

T7 Memory date transfer.

ttl 'lest liternl tttlltll.

Test register gteuter t.liun iiterul.

Mncmonic Getal code Commaud description 04 Test register [or less titaniiiBlfli 24 Test rcgisler less than memory.

16 Test untl"or rnotlity controle.

03 Test or modit'y index.

07 Trans [er register out.

12 Test or transfer register.

THE OPERATION REGISTER Refer again to FIG. 1. The operation register 109may be an llbit flip-flop register 109. The operation register 109 isthe only register in the machine that is loaded directly from the 25-bitWord input from a memory module or from an I/O module. The mostsignificant eleven hits of a 25bit command word coming trom memory andfrom the I/O control modules form the actual command bits of theinstruction word. These 11 bits are fed directly into the operationregister 109. The entire 25-bit word is simultaneously fed into the datainput register 100 and this 25bit word compriseg the 11 most significantbits which are the instruction portion of the word. The 25-bit word alsocomprises one bit which denotes memory module select and a twelvebitadclress portion plus the least significant of the 25 bits which is theparity bit.

In a two-memory module configuration, for example, this memory moduleselect bit could specify Wiiich of the two memory modules is to beaccessed. In the memory module configuration of the illustrativeemhodiment of more than two (eight. for example) as described in thenext section, 3 bits each are in a primary and in a secondary selectionregister to select which one of the eight memory modules is selected foraccess. The memory module select bit provided is bit 11 of the hits inthe address field register 116 word. There are 15 bits in the addressfield register 116. These are bits 9 through 23 of the word from thedata input register 100. These latter 15 bits are the address of theoperand of the instruction before indexing or other modification takesplace. As stated, the 11th bit, the module selcet bit, is the bit usedto select any one of two initiate signals, one selecting memory module 1and the other selecting memory inodule 0. This 11th bit is emplaced alsoin the operation register 109. The module select means and thedescription of the primary and secondary registers will be described inthe next section.

The first six most significant bits of the instruction word specify theparticular instruction. These six bits comprise up to 64 octal wordswhich specify 64 instructions which can be decoded by the commanddecoder and executed. The commands are listed in the previous section.The nonlisted commands are generaly for diagnostic procedure althoughother uses also are contemplated.

The ll-bit instruction portion of the word in the operation register 109is sent to the command decoder 121. The command decoder 121 decodes themost significant 6 bits of the ll-bit instruction portion of the ll-bitword received trom operaiton register 109. The remaining five bits ofthe ll-bit word trom operation register 109 are fed directly to thesubcommand matrix 120.

In addition to decoding the six bits representing the primary commartdfrom the operation register 109, the command decoder 121 also decodessubgroups within the six command bits which, for example, denote whiehgroup of a group of instructions is involved for purposes of similartiming and similar controls.

The address field register 116 sometimes is utilized to insert variationbits into the command word. When so utilized the address field register116 feeds the variation bits into the command decoder 121 and thenceinto the subcommand matrix 120. The command decoder 121 and subcommandmatrix acting together then decode the varied commands specitied by thevariation bits to thereby cause t'he timing and control unit 106 tocontrol the computer mechanism such that the varied command is carriedout. In the absence of a variant syllable inserted by the address fieldregister 116, the principal command, encoded by the command decoder 121from the output of the operation register 109, is routed via thesubcommand matrix 120 to cause timing control unit 106 to set upztppropriate timing and to exercise appropriate control to execute theprincipal command. From the subcommand matrix 120 also are sent signalswhich occur in some commands whic'h inform the I/O modules and thememory modules involved that a word is to be routed from memory via thecomputer to the I/O modules instead of merely to the computer. Also bymeans of the subcommand matrix 120 certain commands may effect thesending of the contents of data to and from the /O control module (orone of the l/O control modules) and the A register 107 or the C register108. The subcommand matrix 120 also specities whether these transfersbetween I/O control modules and either A register 107 or C register 108or memory are data words or are eommand words to the I/O moduleaddressed. That is, transfer can be etected either from the memory orfrom the A register 107 or from the C register 108 to a designated I/Ocontrol module, or transfer can be etiected from a designated I/Ocontrol register to either a memory module, or the A register 107, orthe C register 108 by the subcommand matrix 120 decoding mechanism andthe associated logic in the I/O control modules.

The computer of the present invention can adapt to a clock external tothe computer in the manner set forth in detail in the above referred tocopending application of the same inventors for Central Data Processor,S.N. 521,374, filed concurrently and assigned to the assignee of thisinvention and the contents of which are incorporated herein byreference. The timing and control unit 106 is synchronized to theexternal clock frequency or a multiple or submultiple thereof. Thesynchronization with the external clock usually is governed via the I/Ocontrol module so that the I/O control module is enabled to synchronizememory and computer operations as well as transfer operationstherethrough. This feature is particularly advantageous in that iteliminates the need for a masterand-slave clock procedure and periodicupdating of the various clocks for insuring of synchronization or forspecial timing circuits. This capability of the illustrative embodimentenables synchronzation with various types of inputs whicl1 may beoperating at difierent frequencies; for example, different kinds ofradar or television inputs may be accepted by using the basic clock ofthe input system as the master clock of the present system.

The timing and control unit 106 is also responsive to interrupt signalsfrom the I/O control module. These interrupt signals can specify thatthe next instruction be called from an address supplied directly from anI/O control module to memory. The interrupt signals from the I/O modulesinhibit the program counter 117 from counting and inhibit the output ofthe program counter 117 from being sent to memory during the interruptcycle. The timing control unit 106 responds to the interrupt Signalsfrom the l/O control module by sending to the I/O control module whichsent the interrupt signals a signal which states that the computer isready to receive information from the input/output control module. Asstated, the program counter 117 is not counted or updated during thisperiod and its contents are not transferred out. The timing control unit106 is responsive also to start and stop signals from an I/O controlmodule and also is responsive to various limit, error and testconditions within the central data processor, to vary timing of thecontrol fiip-fiops, etc.

Prnmry and secondary selection registers A feature of the invention isthat a number of memory units may be incorporated in the system andindividually accessed pursuant to commands which contain a number ofbits in the command word, the total count of which bits is less than thenumber of memory units incorporated. By way of specific example theillustrative embodiment of the invention provides that one of aplurality of memory units, up to eight, for example, can be utilized andselectively accessed with only a single bit in the command word. This iseflected by means of the primary and secondary selection registers 119and associated controls and by using the herein described programmingmethod.

The illustrative embodiment provides, for example, a single primaryselection register 119a and a single secondary selection register 1191)and the use of one bit in the command word to specify one of eightmemory modules for any particular instruction. It will be appreciatedthat by the provision of extra bits and tertiary, etc., as well asprimary and secondary registers, a very large number of memory modulescould be selected with a relatively few bits using these features.

Refer again to FIG. 1. Primary selection register 119a comprises a threebit register. Secondary selection register 119b comprises also a threebit register. Since the actual registers are each 3bit conventionalregisters, the details of the bit circuits are not separatelyillustrated and described. Associated controls are provided to loadthese registers with new contents and store the present contents inmemory by variants of the load and store program counter LSP, branch oncontents of memory BCM, and store program counter STP instructions.

The one memory module select bit (which is bit 11 of the instructionword shown in FIG. 2A) specifies that either the primary selectionregister 119a or the secondary selection register 11% of primary andsecondary selection registers 119 is to be used to form the first threebits of the l-bit word to be placed in the address field register 116.The last 12 bits of these 15 bits in the address field register 116 arethe 12 bits from the address sent to the data input register 100. These12 bits inserted into the last 12 bit positions of the address fieldregister 116 are the bits 12 through 23 in the L portion of theinstruction word (see FIG. 2A). The first three bits of the addressinserted in the address field register 116 designate which one of theeight modules is selected for the particular instruction. These threebits are provided into address field register 116 from either the threebits of the primary selection register 1194 or the three bits of thesecondary selection register 119b.

Thus the address generated in the address field register 116 is a l5-bittotal address. The first three bits designate which one of eight memorymodules is selected to supply the data and the next 12 bits determinethe address within the memory module which is to be accessed.

It will be appreciated that any other schemes of addressing whichrequires a total of 15 bits could be used. For example, if desired, asingle memory which utilized 15-bit addresses could be utilized.Although contemplated as within the scope of the present inventon toplace the controls to actually select which one of the memory units ofthe eight units is selected in the processor, the selection may equallybe accomplished by plaeing the actual routing mechanism in the I/Ocontrol moduie as illustrated in the copending patent applicationincorporated herein by reference of Marx et al. for I/O Control Systemfor Electronic Computers, S.N. 527,322 herein referenced to and assignedto the assignee of the present invention.

The loading or changing of the contents of the primary selectionregister 11% and the secondary selection register 119b may be etected inseveral optional ways by the program. One of these methods is by thecommands hereinabove mentioned, namely, the LSP, the BCM and the STPcommands. In the load and store program counter LSP command a data wordis loaded trom memory into the data input register 100, the last 15bits, bits 9 through 23, are loaded into the program counter 117 and thefirst 6 bits, bits 0 through 5, are simultaneously loaded into theprimary selection register 119a and the secondary selection register11922 to form the two new three-bit contents of each of these registers.The former contents of the program counter 117 and of the primary and ofthe secondary selection registers 11% and 11% then are st0redautomatically in memory for future reference.

By the presentation of a BCM command with the proper variant the loadprogram counter operation described hereinabove also is provided. Thatis, the first six bits of the data word are loaded into the primaryselection register 119a and the secondary selection register 119!) andthe last 15 bits are loaded into the program counter 117. In the storeprogram counter STP command, the 6 bits of the primary and secondaryselection registers 11% and 11% (3 bits in each) are automaticallystored in memory.

The first three bits of the address field register 116 in each caseactually determine which memory is selected. These three bits representthe 3-bit contents of the primary selection register 11911 or the 3-bitcontents of the secondary selection register 11% in accordance withwhether the 11th bit of the instruction word is a 0 or a 651.

Two other methods of selecting one memory out of the eight memories areprovided. These may be accomplished by in effect bypassing the primaryand secondary selection registers 119. The first of these two additionalmethods is by indexing. The second of these two additional methods is byindirect addressing.

Refer to FIG. 2C. If an index word contains a 1 in the eighth MS bitposition, the contents of the index word in bits 9 through 11, the MVcontents, are inserted into the first three bits of the address fieldregister 116, replacing the value previously obtained from the primaryselection register 119a or from the secondary selection register 1191).The first three bits of the address field register 116 as in the othercases determine which memory is selected.

Thus, by indexing, it is possible to select a module other than themodule detetmined by the contents of the primary selection register 119aor the secondary selection register 119b by specifying in bits 8 the MSportion, of the contents of the index register that module selection isto take place by indexing and by utilizing the contents of bits 9 to 11,the MV portion of the index register word (see FIG. 2C) to determinewhich one of the 8 modules is selected.

A second method of designating the memory module without utilizing theprimary and secondary selection registers 11901 and 11% is by indirectaddressing. A11 indirect address operations replace all 15 bits of theaddress field register 116 by the 15 bits contained in the L portion,bits 9-23 inclusive, of the indirect address word.

The method of indexing or of indirect addressing t0 determine which oneof the eight modules wiil be selected in the illustrative embodiment isusually performed in operation when an access to a memory unit otherthan the two memory units which are currently being utilized primarilyin the program is to be accessed for one or two or a few commands. It iscontemplated that considerable time will be saved, however, by usuallyutilizing the contents of the primary and secondary selection registers11% and 119b because the saving of time which would otherwise be spentin the indexing and/or indirect cycles is saved. Therefore, in drawingup programs, the programmer normally utilizes the primary and secondaryselection register feature most effectively by having blocks of commandsaccess one of two memories wherever possible.

The primary selection register 119a may be set to bit contents 000 andthe secondary selection register 11912 may be set to hit contents 001 byproviding a clczzr operation which may be eifected by operator control.

13 Timing Refer to FIG. 3. FIG. 3 illustrates the timing counter of theiilustrative embodiment of the invention. The timing counter of FIG. 3is a circuit of the timing and control unit 106 shown in FIG. 1. Thetiming sequence within the CDP is accomplished by the ring counter withmany possible jumps within the ring as shown on FIG. 3. The designationTP in FIG. 3 and in the description herein is an abbreviation for timeperiod.

The ring counter of FIG. 3 eifects the timing sequence and comprises aplurality of flip-flops in ring counter arrangement with attendantcircuitry. These flip-flops comprise two TPX fiip-flops or indexingtiming flip-flops, flip-flops TPX1 and TPX2. Two flip-flops, flipflopsSX and TX are provided and are responsive to the state of flipfiop TPX2to define secondary and tertiary index cycles. A pair of flip-flops,TPI1 and TPI2 are provided and perform the indirect address cycle. Alogic circuit schematically represented as OR gate 0300 is provided. ORgate 0300 is responsive to output of the flip-flop TPX2, or of thesignal TP9-XI or to the output of flipflop TPI2 to start the executionphase. A further OR gate 0301 is provided. OR gate 0301 is responsive toinputs from either flipflop TP7 r flip-flop TPI1 to reset both theflip-flops SX and TX. A pluraiity of flip-flops, flipflops TP1, TP2,TP3, TP4, TP3T, TPS, TP6, TP7, TP8, TP8D and TP9 are provided to performthe execution cyc1e functions. Additionaily, as will be described, apair of start flip-flops, flip-flops TP7S and TP8S, are provided tooperate especialiy during the first fetch cycle following a haltcondition. A Halt flip-flop is provided. When set the Halt fiipflopindicates that the machine has come to a halt. Except for the twocontrol flip-flops, flip-flops SX and TX, one and oniy one flipflop ofthe remaining flipflops of FIG. 3 may be set at any one time. Any othercondition generates a timing error which causes an in:- mediate halt ofthe machine.

There are 17 active timing periods (TP) in addition to the HALT state(18 total). The sequence of the timing counter is controiled by thecontents of the operation (OP) register 109 (FIG. 1), the presence ofindex or in direct address bits, and the contents of various controltest flip-flops. The timing sequence for an instruction may be dividedinto three phases:

(a) The fetch phase, during which a new instruction is read from memoryand placed in the DIR 100 and operation register 109.

(b) The command manipulation phase, during which indexing and indirectaddressing are performed.

(c) The command execution phase.

The fetch phase of each instruction overlaps the execution phase of theproceeding instruction and consists of timing periods TP7, TP8 and TP9.If the computer is starting from the halt state, the fetch phaseconsists of tim ing periods TP7S, TP8S and TP9.

In the designation of timing periods TP7S and TP8S, the S stands forstarting. The periods TP7S and TP8S with relation to the fetch phase areexactly the same as the periods TP7 and TP8 except that no portion of execution of a command may occur during this period. This insures thatoperation up data which is in the operation register 109 will not occurbefore legitimate data is placed therein. This feature eliminates thenecessity for the programmer to have to take special precautions uponstopping and starting.

At timing period TP9, the state of data input register 100 bits 6 and 7are examined to tell whether indexing is required. In the instructionswhich do not permit indexing, this test will yield an automatic negativeresult. In ali other instructions, if either bit (6 or 7) is equa1toone, an index cycle will be initiated.

Still referring to FIG. 3, if an index cyc1e is to be initiated, thesignal X is present (true). If not, this signat is not present (false orThe designations at the upper left of FIG. 3 are as follows:

TP9-I means that if the time TP9 is true, X is false, and I is true,then the indirect address cycle is commenced by going to TPI1. It' TP9-Xare both truc, that is, if at TP9 there is an index, then the indexcycie indicated in the biock TPX1 eommences. Under the conditions at TP9that indexing should not be accornplished, that is, X is false andindirect addressing (I) is false, that is, is not to occur (TP9-), thenthe signai INST is generated which indicates that the machine starts theexecuting phase.

The index cycle consists of timing periods TPX1 and TPX2. During TPX2,DIR bits 6 and 7 are agnin examined to determine if turther indexing isrequired. If so the counter returns to TPX1. That is flip-flop TPX1 isset. At this time the secondary index flip-flop SX is set to indicatethat one full index cycle has already occurred. At the end of asecondary index (TPX2) DIR 100 bits 6 and 7 are once again examined andthe tertiary index flip-flop TX is set to indicate that two fuli indexcycles have been compieted. At the end of the tertiary index cycie(TPX2) the presence of the tertiary index flip-flop TX prevents anyfurther indexing regardless of the states of DIR 100 bits 6 and 7(because the conditions X-TX cannot be satisfied). At this time (TPX2)or at time TP9 (flip-flop TP9 set) or time TPX2 of a previous indexcycie if no urther indexing was specified or allowed, bit 8 of theoriginal instruction word is examined via the flip-flop I (not shown) ofthe timing counter. Bit 8 was previously stored in flip-flop I (notshown). If flipfiop I indicates bit 8 was a one, an indirect addresscycle is initiated.

An indirect address cycie consists of timing periods TPI1 and TPI2. AtTPI2, a new set of up to three index cycies may be initiated byreturning to time TPX]. if DIR 100 bit 6 or 7 is equai to one and ifindexing is aliowed for the instruction being executed. This is becauseflipfiop TPI1 causes flpflops SX and TX to be reset. If no indexing isspecified or aliowcd, further indirect addressing may be specified ifbit 8 (state of flip-flop I) of the indirect address word was equa] toone. This is accomplished by returning to time TPI1. There is no limitto the number of indirect address cycles which may be performed. By thisdevice of permitting indexing following indirect addressing, utmostflexibiiity is provided because both indirect addressing and indexingmay be effected to the utmost depth desired by the programmer. The TPdesignations as TPX], TPX2, etc. are utilized in this section both t0denote the particular flip-flops and the times which are designated bysetting these particular flip-fiops in ring counter arrangement.

If at times TP9, TPX2, or TPI2 no further indexing is specified orailowed and no further indirect addrcssing is specified. the signal INSTwill be generated. This signai indicates that the timing counter willnow proceed to the command execution phase. If the operation register109 now contains an instruction in the control group, the timing counterwill proceed to time TP7. If the operation contains a command not in thecontrol group, the timing counter (FIG. 3) will proceed to time TP1,

The control group is defined as al] of the instructions which do notrequire a data word from memory. That is, these instructions are thosewhich do not require the reading trom or the writing into memory of adata word. They are identifiabie by the fact that the operation code foreach of these instructions starts with 00. These instructions generallyare the instructions which do not require an operand. These commandsinclude Add Literal, ADL, Branch Conditional, BON, Branch Unconditional,BUN, Control Descriptor Transfer, CDT, Reset Register Bits Literal, BRL,Reset and/or Shift Register, RSR, Sub tract Literal, SRL, SubregisterBits Literal, SBL, Test Literal Equai, TLE, Test Register Greater ThanLiteral, TLG, Test Register for Less Than Literal, TLL, Test and/orModiiy Controls, TMC, Transfer Register Out, TRO, and Test or TransferRegister, TTR. This is shown in FIG. 3 by the input INST-CG to flipflopTP1. From this point the sequence of the timing counter, FIG. 3, iscontrolled by the instruction in the operation register 109 and varioustests and limit conditions.

Referring to the lower half of FIG. 3 there is shown generally in thisportion the timing circuitry involved in the execution of the variouscommands of the computer. The specific timing for each command may bederived from a section hereinbelow setting forth the Central DataProcessor Equations. The timing of any particular command may be derivedreadily with reference to that section. However, a general descriptionof the timing involved for any command is presented at this point.

Upon the occurrence of an instruction which is not an instruction of thecontrol gronp, flip-flop TP1 is set indicating time period 1. At timeTP1, if the command is one of (1) the read group RG or (2) one of thecommands for set index location register SXL or (3) store C counter or(4) store register, then a jump is executed to time period 7 by settingthe TP7 fiipflop. The read group instructins are a number ofinstructions which may start with a ()1 as the first two bits of thecommand code. These instructions are TDO, TEQ, TLT, TGT, TIR, BOM, ADD,SUB, MUL, DIV, SRB, RRB, LXL, and LDR. If the command is one ofmultiply, or divide, or reset shift register, that is, MUL, or DIV, orRSR, then a jump is made by setting the flip-flop TP8D. The flip-flopTP8D is maintained in set condition if the instruction is not the Divideinstruction, that is, if it is either MUL or RSR. This occurs by thepresence of the MTP8 signal generated by the control logic. This settingof flip-flop TP8D is maintained in this manner for iterative operationsincluding multiply and reset for shift register. In the case of Divide,however, a two-step iterative procedure is eiected. A jump is made fromflip-flop TP8D set to the time period 8 and fiipflop TP8 is set. Then,iteratively, as shown by the return line, a jump is made back to settingof flip-flop TP8D again. The number of iterative cycles is governed bythe counting of the last six bits of the address field register 116 (secFIG. 1) under the direction of the timing and control logic 106. Whenthe interative cycle is complete, as indicated by the presence of asignal MTP8' (the prime after 8 means not) then the jump is made againto the flip-flop TP8 and from that to the flip-flop TP9 which when setintroduces time period 9. At time TP9 the execution of any instructionin the machine is complete and the overlapping fetch phase has placecl anew instruction in the operation register 109. (Sec FIG. 1.) At timeTP7, if the commancl is other than a multiply or divide or reset orshift register, than a jump is made to time period TP8 and thence totime period TP9 for completing the execution of this command. If theinstruction originally was in the control group, then an immediate jumpis made to time period TP7 which is at the start of the execution cycle.As before, the command is executed cluring sequential time periods TP8and TP9. If the instruction is not in the control group but is one ofthe instructions for block test, BT or test or modify index register,TMX or add and store, AOS or double precision, DP, then following timeperiod TP1 a jump is made to time period TP2 and sequentially to TP3.That is, it the signal is on block test BT which comprises the threeblock test signals, that is, if it is either BTE, BTL or BTG or it thesignal is TMX or if the signal is an add and store, AOS which comprisesABS and SBS, or if the signal is a double precision DP signal whichcomprises DPA and DPS, then a jump is executed to the time period TP2and thence to time period TP3. As will be shown hereinafter, the settingof these time period flipfiops enables the various control circuits toperform the necessary logic operations to execute these commands. Attime period TP3, if the command is a block test commund, and theinternal jump control, IJC

flip-flop, has not been set by test conditions in the previous timingperiods, then a jump is made to time period TP3T. If the bounds have notbeen exceeded, the Limit (limit not) signal causes a jump to time periodTP4 and thence recycling is ettected to time period TP1. In this mannerthe procedure is iterative until the bound has been met or exceeded,which is denoted by the presence of a Limit signal. Upon reaching theboundary and the Limit signal being eflected, a jump is made from timeperiod TP3T to time period TP7 and conclusion of execution is made intime periods TP8 and TP9.

If at time period TP3 a block test is not being executed or it a blocktest is being executed, the flip-flop IJC is set, then a jump is made totime period TP5 and from thence to time period TP6. Thence trom timeperiod TP6 the jump is made successively to time periods TP7, TP8 andTP9 for execution of these commands.

If the signal into flipflop TP1 is not one of the RG or SXL or STP orSTR signals, and also, is not one of the BT or TMX or AOS or DP signals,then a jump is made from time period TP1 to time period TP5. It isassumed that the signaal is also not in the control group, since in allcontrol group signals entry is not made into flip-flop TP1 bilt is madeinto execution immediately by jump to time period TP7. If the jump wasmade from time period TP1 and if a normalized register command isinvolved, at time period TPS the signal MTP5 is generated by the controllogic until the normalized condition is met. That is, until thecondition of normalizing has been met, en MTP5 signal will continue tobe generated and recycling by repeatedly setting time period flip-flopTP5 will permit the reiterative operation to occur. When the normalizingcondition has been met or When the limit placed by the hardware on thiscount is reached, a jump is made to TP6. Following this successive jumpto the time periods TP7, TP8 and TP9 are efiected during whichsequential time periods the remainder of the instruction is executed. Attime period TP9 as usual the instruction is complete, and the nextinstruction is then executed.

Referring to the output of the time period flip-flop TP9, in some caseswhere it is desired to halt the computer a Wait signal is generated Whenthis Wait signal is present and was present from a time before thesetting of time period flip-flop TP9, then the Allow-Halt flip-flop (notnumbered nor illustrated as a block) is set. If the Allow Halt flip-flopis set at time period TP9 and the Wait signal is still present, then aHalt will be generated. This is done by setting the Halt flip-flop. AWait signal maintains the Halt flip-flop in halt condition until theWait signal is removed. The Wait signal is generated in one of the I/Ocontrol modules of the copending patent applicatiou being filed of H. B.Marx et al. for I/O Control System for Electronic Computers, Ser. No.527,322, hereinabove referred to and can be caused by inputs fromswitches or peripheral desices or control logic within the module itselffor diagnustc purposes, for halting the computer at the end of anoperation, or for halting the computer in order to allow the I/O controlmodule to exercise special functions, including the aforementioneddiagnostic procedures. When the Wait command signal disappears asindicated by the Walt (weit not) signal a jump is made to time periodflip-flop TP7S and thence to flip-flop TP8S following which the jump ismade to TP9. The setting of these flipflops initiates the RestartControl Logic so that during time periods TP7 S and TP8S the nextinstruction is read trom memory, and following the jump to time periodTP9 the next instruction may then be executed.

When the time period flip-flops TP7S and TP8S are activated, that is,during the Halt procedure, the flip-flop TP9 circuit does not etectcontrol to complete execution of a command. The only action occurring inthat case during the three time periods TP7S, TP8S and TP9 is to fetchthe next instruction trom memory. It should be remembered that thepresent instruction was completed before going to Halt. This circuitrymerely prevents execution of commands previously in the register andpermits the computer to restart on the next sequential instruction afterthe reason for the halt has been corrected.

Restating, in the execution of any instruction, when timing period TP8is reached and is not a part of an irrterative cycle, the ALLOW HALTflipflop will be set if there is a WAIT signal present (trom logic inthe I/O). The ALLOW HALT flip-flop indicates that the computer will haltat the completion of the execution of the present instruction. At timingperiod TP9, which is the last timing period in the command executionphase, the presence of the WAIT signal from the I/O and the ALLOW HALTflip-flop cause the computer to go to the HALT state. The computer wil]remain in the halt state until removal of the WAIT signal from the I/Ocauses it to go to TP7S and start the fetch phase of a new instruction.

The following recapitulation relates the phases to the time periods andthe description of the timing counts circuits of FIG. 3.

Fetclz Phase.ln the fetch phase of the timing se quence, a newnstruction is read trom memory anti placed in the data input registerand the operation register. The timing periods and actions reiating tothis step are listed bclow:

inrlexing or indirect addrnssing.

Command Manpulaton Plm.re.-The command manipulation phase provides forindexing and indirect addressing. At time period TP9 a decision is madeas to the type of command manipulation required. Unless a nonindexableinstruction (TMX. NMR, LSP, or MDT) is specified, up to three cycles ofindexing may be done The primary index cycle adds the value of theaddress in the specified index register to the address of theinstruction and uses the result as the new instructin address. Also atthis time, the module valuc (three most significant bits of theacldress) may be modified if the most significant bit of the index wordis a one. If the primary index specifies a second index cycle, the indexcycle will repeat, adding the specified register to the new instructionaddress to form anotiier new address (the module value may again bemodified). In a similar manner. a tertiary index cycle will beperformed, if specifieci No further indexing is allowed after thetertiary cycle, even if the tertiary index specifies further indexing.

If indirect addressing is specifide in a command and indexing iscomplete, the instruction address (modified) wil] now be uscd to ohtainan indirect address. An indirect address may specify an index (up to 3cycles), or a second indirect address, and the process will continueuntil n0 further indirect addressing or indexing is specified. At thistime, the computer will proceed to the command execution sequence. Thefollowing table lists the timing periods relating to the commandmanipulation phase:

Command Execution Plmse.-The following table lists the timing periodsand action relating to the command execution phasc. The list is providedas a general guide, and the equations whereby the individual algorithmsfor indexing anti indirect addressing may be derived readily should beconsulted for specific actions at any given timing period.

Timing ieriod Action 'I P1 Rond flii: (front memory or I,;O, or storedata. 'Il2 0pemte 011 data. Tl3 Rcnrl limit value for bleek tests,OIBI'WSG opernto en data. 'Il3'l ,T6St for limit (lilock test only).'IP4 Form nddrcss of next d:itn \\orrl [lilock test onl,v)

nlodilication for liext instruction, STEP P un1ess hnlting ur mecuting aprogram interrupt.

HALT No netion. Extcrrr.rl (l/ or progrtnmncrs panel seloction niregister gnted into the DOM or MAM anti e\tern:ii control of theI"eounter 1ro ullowed (for dingnostic and londing purposcs). If thevmit" sign;il is removed nnd the sign:rls CLEAR nnd TER nre nhsnnt,procue l to TPTS.

TPTS Restxnt cyclo, Stld l-count u idress to memory nl1 ini ite l't!l.d.

TP8S.. Rostsrt cycle, rnnd instrnction, 311d proceerl t 0 IP9.

SXF Flipilop is set ut the end of the tirst index cycle.

Wit! bc reset during indirect nddress eyclo t[ nny) at '1l11, urtlilring eoinin;rnd execution :it 'IPT.

'IXF Fliptlop is set t the end of the secomt index cyclc. When 'IX t ispresent, nu turther index cycles nnty he eiccuteti. \\"ill l:e resetdnring indirect nddrcss cycle til nm) nt liFl or duriug coninmndexecution nt tl7.

N0w refer to FIGS. 4A, 4B, 4C and 4D, FIG. 4A is a chart comprisingboxes and represents the commands plotted against the timing periodsduring which execution of portions of the commands of the computer arecarried out. FIG. 43 is a chart illustrating u typicnl indcxingoperation. F1G. 4C is a chnrt illustrating n typical indirect addressingoperation. FIG. 4D is a chart illustrating the key to the diierent boxesin various operations. In some cascs timing periods ure repeated. Forexnmple, 2 is repeated thrice as are time periods 5, 7 and 9. Therez1son for these repetitions is lhat the computer of the presentinvention synchronizes and ldjusts to any external clock arrangement,and it also adjusts itself to be utilized with vnrious types of memory.For use with various speeds of memory operations or for different clockfrequencies or durntions for the external clock, the computer beingsyncltronous performs no fnnctions until the ensuing clock pulse occurs.Therefore, for cxample, the three 2s are represented in FIG. 4 by way ofillustration in operating from a one-megacycle clock. The computer wouldsee timing period 2 as being 3 microseconds long rather thnn as Imicrosecond since, by way of exnmple, this particular chart was made upfor a memory which requires 4 microscconds for the memory cyclc.Obviously, working with different memories these time-awaiting periodswould be varied accordingly. As shown in the Key of FIG. 4D, the boxesin sereen pattern denote Reed operations. The boxes with horizontalhutching denote write operations. 'lhe vertically hatchecl boxes denoteoperate." The blank boxes are for unused time periods in executinginstructions. The cross-hatched boxes denote pause. All por tions of therepeated periods except the last are referred to as pauses on the chartsof FIGS. 4A, 4B and 4C.

As far as the Centra] Data Processor is concerned, it does not know thatthese pnuses are there. However, the pauscs relate the operation of theCentral Data Processor through a consistently running one-megacycleclock. Therefore, for example, the timing period flip-flop TP1 is set atthe first count of the one-rnegacycle external clock. the flip-flop TP2is set at the end of one microsecond of the external clock, but theflip-flop TP3 is not set untii the actual fourth clock pulse from theexternal clock. However, insofar {is the computer is concemed, itrecognizes this as the third clock beat. Similarly, the flip-flop TP4 isset at a one-microsecond external clock seventh count although withinitseif this is recognized by the computer only as its fourth count. Theensuing discussion assumes that the instruction goes through each of thetiming period counts, that is, TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8and TP9. However, actually jumps are made in accordance with therequirements for control functions exercised by the computer for eachdifferent command. Because of these jumps the necessary iength of thepauses vary. This is because in the case of some com mands the computermechanism only requires a memory cycle once every severai timingperiods, for example, tour timing periods, in which case amultimegacycle such as a four-megacycle memory cycle could be executedwithout pauses. Using the same memory with a command having only threetiming periods between memory access cycles only one pause period wouldbe required. Correspondingly, the number of pause periods varies bothtrom command to command and in accordance with the length of time that amemory cycle takes to be completed. This chart is made up mereiy by wayof example for a fourmicrosecond memory cycle. For example, referring totiming period TP7, it is seenthat it can be repeated three times forsuch a memory cycle although, for exampie, for the TIR instruction onlyone micrsecond is required for execution in the seventh timing period.Therefore no delay need be instituted, but during the next clock pulseafter TP7 is set the entire execution of the command insofar as the TP7period is concerned is compieted within that one micr0second. The Read,which is represented by screen pattern boxes, is just an indication oftime at which data is received trom memory. Similarly, the blocks orboxes with horizontal hatching indicating the Write operation show timesat which data is set to memory. The vertically hatched boxrepresentations of Operate periods represent times at which operationsother than reading or writing are taking place.

The blank white blocks or boxes denote unused timing pulses, that is,timing puises which do not occur in the particular command because ofthe jumps in timing which are instituted in the operation of thevarious, commands. The white or unused block ndicates that this commandis not using the functions which are then created by setting thesubcommand matrix 120 -controi gates accordingiy. For this reason inperforming the commands the jump is effected from the last marked in boxto the TP Set time in executing the commands. That is, in executing thecommand whenever a masked sereen pattern, horizontal hatched or verticalhatched block is ended and an unused blank block starts there is animmediate setting of the next TP flip-flop corresponding to the nextmarked box (except cross hatched pause) indicating a subsequentoperation. The cross hatched box pause representations may be requiredbecause it takes some time to ready the memory to send to the computerand memory may or may not be ready to send. For example only the firsttwo time periods are required since as far as the computer knows, itreceives anything it requests fr0rn memory at time period TP7. That is,the computer is pausing during the first seven TP period clock pulsesbecause it does not receive these clock puises from the external clock.This masking is done in special control logic of the I/O Controi Moduleof the aforementioned accompanying patent application of H. B. Marx,Ser. No. 527,322. When a particular timing pulse or a group of timingpulses are repeated in a given instruction, for example, for theinterative procedure in Multiply, this is denoted by the slanted,blackened bottom corners of the appropriate boxes as iilustratedadjacent Repeat in the key illustrated for interpreting the varioustypes of boxes in FIG. 4D. Simiiarly, in the case of repcats where thisrefers to a group of timing pulses, this is indicated by a dark righttriangle having a negative sloped hypotenuse in the left lower corner ofthe first of a series of boxes and a dark right triangle havng apositive sloped hypotenuse in the lower right corner of the last of theseries of boxes. T his series of boxes forms the repeated timing pulseswhich are reiteratively eiected by the command.

Due to the fact that indexing and indirect addressing are optional forany instruction and are under the control of the programmer, a typicalindex cycle is presented in FIG. 4B and a typical indirect address cycleis presented in FIG. 4C. Indexing and indirect addressing are optionailyefiected. The timing anti control sequence of intlexing and indirectaddressing in TPX1 and TPX2 and in TPI1 and TPI2 times has been coveredhercinabove. All indexing and indirect addressing is done after the lasttiming period TP9 of the preceding command and before the execution ofthe instruction at timing period TP1 of the command presently to beexecuted except in the case of certain commands or in the case ofcontrol group commands in which indirect addressing operations areeffected at time period TP7. FlG. 3 of the drawings describedhereinabove illustrates the sequence of activation of the TP flip-flopsfor each of the commands of the illustrative embodiment machine.

From the above disclosure of timing interreiationships and the centraldata processor logic equations which will be set forth hereinbelow theiliustrative embodiment central data processor of the invention and itslogic and electrical circuits and structure are constructed readily bythese skilled in the art. The timing is included a1so in thesecquations. However, t0 insure convenience of duplication of theinvention by others, the teaching herein is amplified by presentingfirst a section on definitions to facilitate understanding by dcfiningthe commands, subcommands, signals, flipflops and other components,registers, logic operations required, etc. The centra] data processorequations are then given from which the algorithms, the logic circuitsand corresponding electrical circuits and the structure of theillustrative embodiment machine may be constructed readily. In order toiliustrate the building of the structure of the iliustrative embodimentconveniently, a typical command, ts timing periods and the subcommandsnccessary to effect it, that is, the algorithm are illustrated by way ofexample. Further, the utilization of subcommands in the equations isexemplified by describing generation of the DESEN subcommand and the subcommand A TRPM with relation to the involved equation. Following this,the unconventional new logic circuits associatcd with the command andsubcommand uigorithms are specifically illustrated in FIGS. 5, 6, 7, 8and 9, and the figures are each described in detail. A derivation ofcommands and variations which may be made by the programmer in operatingthe computer of the illustrative embodiment of the inventio-n is thengiven. Thus the description herein insures cool; book presentation toone skilled in the art.

DICTIONARY OF CENTRAL DATA PROCESSOR TER.\IS

Signal D elinition Ad) to A23 Outputs of the flip-flops of A register.ADDA Transfer sum to A register.

Transfer sum 4 to sign bit; of A register.

ADDC Transfer sum t0 C register.

ADDC Transfer sum 4 to sign bit; of C register.

AH-.... Allow halt.

ANDA Enabies logica] AND ot the A register and the outputs of the adderand transfers result to the A register.

ANDC Enables logical AND of the 0 register and the outputs of the adderand transfers result to the C register.

AOS Add and store or subtraet, and store (ADS+SBS).

API Ailow program interrupt.

AS Single precision arithrnetic operation (ADL+SBL+ADD+ADS+SBS).

ASO Non-storing arithmetic oporation (ADL +SBL+ADD+S UB).

ASOF Single ASO is delayed by one clock puise (used at TP9).

Signal Definition Signnl Definition AoA Combination of TIREFXZ t gcnor-ENP Flip-flop which enahles P counter and ate ADDA and ADDAq. tlio I/Ocount bits to the data output AB Combination of SRS-TP te generatomultiplex.

ADDAADDC,ADDA4IJMADDC. ENPIAD Flip-flop signal whlch onablos programAqbC Combination of (SRL+SRB)-TPT t0 intcrrupt address to tlie memory udgrnerato ADDA, ADDC, ADDAQI, dress register. and ADDC4 ENSR Flip-flopsignal wllich cnnbles module A D Combination of LDRTPT to generatoselection register PSR end SSR bits ADDA, ADDC, ADDA, and to the dataoutput multiplex. A)DC. ENXL Flip-flop signal which EllllltS tlm intlcxAdE Comblnation of TIR-EJ-TIT t0 locati0n register to tlie data output.

generatc ADDC and ADDC S. EOq to E023 Exclusive OR outputs of the trststnge AoF. Combination of LCATP5 to generate 01' tlie adder.

ADDC and ADDC4 F9 t0 F23 Outputs of the uddress feld register. BCMcontems of memory 1) Curry condition betwccn stages of tlie F BCNColiditionol brunch instruction. BCT Instruction group of DUN, BON,"PRO, FCAR1' cou.nmr c(mmlned m the addmss field or 0D'1, FCAR2D reglsm"BT Block test grouping of BTE, BTL, 01 HAC Halt nnd allowcontrollnstructionwhich BIG. enables external control of memory BUN.Unconditional branch instruction. address multiplex transfers wiiile inC4: to (123.. 0utputs oi flip-flops o[ the C register. HALT state i1''IP is not present. CARL. HALT Flipfiop whicl1 linltS tlie timingcounter CAR7. in its inactivc state. CA R12 C arry signnls bctwccnstages of the adder. HALT E0 Flip-flop Wliich cnubles halt signnl to LO.CARi3 2. HIC "Halt and I/0 control" instruction wlrich enubles extcrnalcontrol of data output multiplex transfers wi1en in the HALT state endwhon ENDIRDOM is not present. I Indirect uddress oycle requircd. IDDSignul indienting indirect data descriptor level te I/O during anyinstruction Clcar error ilip-lops. with indirect nddress bit equul to 1.CLOCK DEN Flintlop slgnnl ennblss input data t0 l COMP Flipflop whiehenahles complement out UC Internal jump control Hip-flop.

puts of the data output multiplex. N C Signol designating command poritycrror COUNT F Count signal to F register (count up). indicator output.CPE Comniancl pnrity error flip-flop. INDD E Indicator signuldvsignuting dein parity CPERROR Command pnrity signal to I/O (om erroron programmer's panel.

clnck pulse). INDEJC Indicator signal desigusting extornai DESENDcscriptor enablc te I/O (Accept data jump contr0l 0n pr0granunerspanel.

trom dato output multiplex). I DITC Indicator Signnl dcsignatinginternnl DIM4 t0 DIM24 Data input liues frorn 1/0 te tlie data jumpcontrolon progrnmmer's panel.

input multiplex. DIPE Indicator signol dcsignoting I.i purity DIR toDIR24 Outputs of the flip-flops of the data. error on programmers panel.

input register. INDMAMO to INDMAMZ3. Indicator signnl designntingflip-flop out- DIR to DIR24 Outputs of the flip-flops of the data puts01 the memory address multiplex input register. on progrununurs panel.DIRB to DIR24; Flip-flops which ennlile parity check. O t0 INDMQ4Indicator signnl dusignnting flip-flop out- DIRADI ..lEnables mostsignificant half of data puts of tl1o data output multiplex on DIRADIinput register to adder. progrmnmer's panel. DIRAD2, Enables loostsignificant half of data DOP t0 INDPO1O Indicator slgnal on programmcrspanol input register to adder. dnsignnting flip-Hop outpllts of tlil)lvision lnstruction. operation register. DIVF Delays signnl DIV oneclock time at TPD. INDOVA Indicates A register overflow on pro- DMRCombination of MUL, DIV, er RSR. grmnmers pnncl. DP Double procisionoperation (DPA 0r "C Indictcs C register overflow on pro- DPS).g'rammer'5 panel. DPA Double precision add. INDPC1 iO INDPC5 Indicatesoutputs of program controi bits DIE Data parity error flip-110133. 0nprogrammers panel. DPERRO R Flip-flop which initiates data pority INDTERIndicates timing error output 0u pro signal to I/O (ons clock time).grammers panel. DP Dc1ayg doub1e precis1on pmmm signa INST Timing countWhch prewdes wnml One clock time at TP9. execution of an instruction.

4 n m n r double pm on su m g g g i,fgjf ff i f fi EAC Carry Output mostSignificant bit LCA Load 0 and A gister instruction.

adders LDR Lood register trom memory instruction. EJC Extemal P 50mm! lLIM63 Si): lcast significant bits of the F counter ENA Flip-flop whichenebles A register to the have reached "311 01105" limit.

data output multiplex. 65 NT C0mbnation Of LSP, MD'I, NMR, 01' ENCFllpflop which enables C register to TMX instructions data Outputmumplex. LSP Load anrl store P connt instrnction. ENDIRI Flip flop Sigmlwmch enables most LXL Lld index locat1on register instruction. 9 t0 MM24.... Output of the memory [nidress multiplex micant half of the datainput register to 10 1/0. the (ata output mumplex' MCS Initiates memoryqycle start, m I D RZ Flip-flop which enables least significant memm-ycontm1 hall of the data input register to the MDT. Memory data transterinstruction. data output multiplex. Most significant P count siguul tiIIO. ENF Flip-flop whiclienables address filed rag MTP5 Maintains timingcounter in time ll ister to the data output multiplex. tat

Signal Definition Signal Definitien MTP8 Mainteins timing counter in theTP8 SIIRA. Component i SHRA.

state. SHRO Signal wlxich e.llows right shift of the MUD Instruetiongroup of MUL er DIV. register.

Multiplyinstruction. SP9 te SP%.... Signel which sets or holds output ofP NCO No charecter option avoilable on data counter (also used by memoryB.ddrcss trom memory. multiplex).

Norrneiize register instruction. SR Instruct'ion groups SRL, SRB, er SRSNormolize test conditions met. SRB Set register bits instruction.

NZ Checks i'or zero resuit irom arthmeti0 10 SRL- Set register bits tromliteral instruction. operation. SRR Instruction groups SRL, RRL, SRB,

UDEN Output data enabie to I/O. RRB, SRS, er RRS.

OP4 t 0P10 Outputs of opcra.tion register flip-iouS. SRS Set registerbits and store instruction.

OP1OF Dola.ys 0P10 flip-flop output ne Glo SSR1 te SSR3 Outputs of thesecondnry module selectime et Il9. tien register.

OV Flip-flop which centains overflow blt STEP Signei which advances theP counter.

irom erithmetic operations. STORM Flipfiop which initiates store modeOVA A register overflow flip-flop. signal te memory.

OVC C register overflow flip-flop. Store P-count instruction.

P9 te P23 Flip-flop outputs of the program Counter Set timing periodTPIi to the 1/0. 90 STPXI Set timing period TPXI.

PAR; te Ii'iR23 Data output multiplex signal to t S'II2 pnritygenerator. STP3T PARITY Signai which indicates that the word in SIPeSignals which cause the timing counter the dutninput register hascorrect (odd) STP7 to advance to the respective timing parity. STP8period.

PC1 to PC5 Output of program controi flip-flops. 25 STI8D PCARI1 SIPQPCARI4 STB. Store A or C register instructon.

PCAR17...... Cmn slgnals Wnhm the P counter STROBE A.. .lSignni whichcauses A register Fiipilops PCAR2O STRO BE A i to accept input data.

PSR1 te PS R3 Outputs of the primary module selt ti n STROBE .4 Sigma]which causes t1ie sign bit of the A register. register to accept inputdata.

R Signol iovcl to tho I/O W w evcr OP9 STROBE C }Signal which causestlie C register Flipis in the one state. STROBE C flops to accept inputdata.

RCHK1 Register Ohk i0r fili 0l1S l'0 S'IROBE Cqi Sgne.l which causes thesign bit 0[ the C stage of adder). register te accept input data.

RESET FL Reset sx leest significant bits o dd fl STROBE DIR, Signalwhich ce.uses the data input ficld rcgistel. S'I RODE DIR register toaccept iniormatioriiror1i ths RESET FM Reset bits 1247 of the eddressfle l STROBE DIR data input multiplex.

rogister- SIROBE OP Signaiwhich causes the operation register RESET FMSBReset three most significant bits of th to accept input data.

sddress fieid register. STROBE X Signal which oauses the operation reg-RESET P Reset bits 12-23 of the P-countsr. 4 ister i'0 accept input datafr0m bits 6.

RESET PM Reset threc most significant bits of h 7, and 8 (index andindirect address). Pcounter STROBE XL..- }Signal which causcs the indexlocation RG Reed gmup. STROBE XLr. register to accept input data.

Iustruction groups RRL. RRB.0r R STRUE Signal which sets the data outputmulti Reset register bits. plex TRUE flip-flop.Resetregsterbitswithliteralinstr l n SUM4 te SUM2B Outputs of the adder.

Reset register bits nd StOXB SXF Output oi secondary index flip-flop.Reset end/or shift register instruotio SXL Sto index location registerinstruction. Redw' itc gro p 2 ICL Signal whieh clea.rs the timingpl1lse SCA Store C nd A regis ers H counter when "cleer" or timing errorSCCO Sign control IOi data output U D signals arn present.

COM g 1. TDO Transfer data te output instruction.

SCF Sl'gn control flip-flop ussd durl i: arth- TE Test rol equal(instruction gioups 'ILE,

metic operetions. TE Or ET SCTR Sign C0nti0l for data output 1D be resetby clear" signal).

TRUE gfl TERROR Timing error signaal te 1/0.

SF9 OSF23 Signal W i( h SGS h0lds op 'IG Test for groeter (instructiongroups address iieid register (also uscd by TLG, 'IGT, er BTG). m moryaddr ssmul p l TIM Transfer input to memory instruction.

SHAi Condition ior setting one bit of th A '11E Transfer Input m A or 0register inregister during a shift operetion. (30 Structon S1IA23C0nditi0n Setti g it 23 0f 1 TL Test, {01' lees (instruction groups TLL,

register during a shift operation. 'ILT, er BTL).

cnd.mon semng, blt of C TMC Test end/or 1nodfy controle instruction.

register during 9. sluit right eperatron.

SHC1 Conditjon {or setting bit one of the C TMCR hp"flOps specmed by TMCregister during e shift right operation. 5 mstmcumx sgnz3 Condition forsetting bit 23 of the 0 'IMX T st nd/er m di y ind x r gist r i11-registur during e. shift left operation. struction.

SIIIFT Sign l used in the g i n of Sh[t TN lnstructen g'rouping ()TTRand 0I1o. Q0mllmds dllirlg RSR TOP Instruction grouping of TTR and0Pll).

SI1LA SLUE WCI BW5 l Shirt the A TP1 T'uning (munt (wad O1 store datg]register.

SIILC Sgnal which allows a leit shift of thc C TP2 Tlmng count (Operatedam) gisten TI3 Timing count (reed limit value er con- S] iRA Signalwhich aliowsaright shift of tllc A Il3'l Timing count (test i'0r limitvalueregister. block test ouly).

Signal Definition Signal l)efinition TP4 Timing count (eddress next dataword- V Signai which is used as 8 level to the blk test r) I"o WICIIGVIbit P10 is in the oue 'IP5 Timing count, (operate en data-eend sta,tg

t ddr t y). WG write gmu (OP5OP1L TPG d (Store data Or lend scmnd XSignn.l whih indicutes that an index cyele is te be executed. Tmnng munt(Opmt dam W0rd XL9 tQXL21 Flip-flop outpuis of the index locntiou end/orSmid P address to memory). register TP7S Start timing, eount eycie (eendP address m Th 1/0 1 d i h b b f TP8 Timing Lount (operate on dataend/or e contro m9 u e terms w 1c n1ay e 0 mad msmwmn Wmd) terest may beobtamed from the aforemennoned copend- TP8D Timing count {peiformiterative op ing patent application of Hans B. Marx er al. for Input/erations). Output Control Systern for Efectronic Computers, S.N. Smrttiming c0l1nt Y n5truc 527,322, assgned to the assignee of the presentinvention, and the disclosure of which is incorporated herein by TP9'Iuniug eount (finai step of prevlous reference' (indirect addmss readThe equations from Which the illustratve ernbodime nt Timing munt(indirect address mimip. of the computer of the present mventron may bebuilt ii are as follows: TPX1 Timing count (index reed). TPX2 Timingeount (index rimnipulation). CENTRAL DATA PROCESSOR TRDF Transferaddress of data input register LOGIC EQUATIONS Elddress fied registerThis seclion contains the logic equations associated TRDP f data regxsmwith signals generated or otherwise used in the central TRFM Speeifiestransfer of address from address data processor for command Thefono\ylng fie1d gister m me memory address rules appiy for the propermierpretatron of this sectton: multiplex. (1) The set and reset offlipflops are shown as /S aud TRINSTM .1Speeifies transfer ofinstructinn uddrlS /R. 'IRINSTM t0 memory 'IRMSBP Transfer ouput of hits9, 10 and 11 Of EX:

the adder to the most significant bits Set A10 is AIO/S 0 the Reset Ali)is AIO/R 'IRMVF Transfer tlie module value of hits 9 10 and 11 f t datai put register t (2) The CLOCK sigma] appears in an equation for f l d tof the set or reset of a flip-flop oniy when it is gated with other e sinais and th c bnatio 0 TRO Transfer register out instrnction. isclockede g TRPM Signai which specifies transfer of P- counter input datato the memory pear In the equatlon' address i 1|) (3) Dash numbers(1.e., 1 2 etc.) are used to show 'IRPSF SDECS tiie transfer Of theprimary identcal logic signais being driven by different elements.module seiection register its t t Dash numbers are not needecf for alogic evaluation. most Significant bits I(IPSS The excepton occurs whenthe signal appears oniy with TRPXM Specifies the transfer of the indexva1ue a dash number.

front bits OP7 and OI8 to the leest Significant hits of memory addmss 4)An asterisk precedmg a s 1gnai or group of s ignals mulfiplex desrgnatesthe negattorr o f th it signal or group of signals. TRSFL Specifics htransfer idtiirrm adder A logfcal AND Slgl 1S lndlcated y Perl0d outputs(bits was} to the Siii' irast tween the symbols (e.g., A-B). significanthits of the Bddl'eS Held (6) A grouping 01 rnultpie grouping of logicterms register. is shown with parentheses only; e.g., (A(B+A)). TRSFMSpecifies the transfer of data from adder 00 h sgnals affected outputs(bits 12-17) to tiie eddress fieid regi r (h ADDAO STROBE CO TRSM.Speciies the transfer of output date ADDCO SHCO g lligllxaddll to thememory eddress AO/R DIMO TRSM+TRFM Enables module vulue fr0m addressfi0ld AO/S DIRO register to the memory address multi- SUMO DOMO piexSTROBEAO FARO 'IRSP Specifies the transfer of output data OPO EOO fromthe adder to the Peounter (12 AOA.AOF bits). TRSSF Speeifies thetransfer of data from the A1)DA *OPQF(TP5 SCF*OV AOS SRS) seoondarymodule selection register to +TP3A OS+ ftllodigiiscllllficint bit of theaddress ADDAZTP7(LDR+SRL+SRB) +ASOF 'IRUE Flip-{iep which enebles theTRUE (TP8+TP9'SCF'*OV)) outputs of the data output multiplex. 'IRXMSpeeifies transfer of data irom the index +CI.MUL

iocetiorr register to the memory address A DDA :OPIUTD8+DPF(TPS+ TP7+TP9) multipiex (bits 921). +TP7(LCA+ T g 0 p ITLETLL ADDA=(TIR *EJCFIZ)+( TNP FJ5 FJZ)) m ADDAO=TP7.(AA +LCA)+*OP9F Timing Ior sign controlcircuits. (AC'I'AOD+AOB+(NZ T'IB. Test andior transfer register iustrucADDAO:+SCFOV)( OPIOF+NZ) tims (ASOF.TP9+AOS.TP5))+ TXF Thl'd indexflip-flop siguai Wllh pre- ADDAO=TP7.FI6.FIZ.TNP+TP8.DP

vents further indexing. (*OPIQF+NZ)+TP7 MUL

